<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>MOV (predicate, predicated, merging)</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">MOV (predicate, predicated, merging)</h2><p>Move predicates (merging)</p>
      <p class="aml">Read active elements from the source predicate and place in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register remain unmodified. Does not set the condition flags.</p>
    <p>
        This is an alias of
        <a href="sel_p_p_pp.html">SEL (predicates)</a>.
        This means:
      </p><ul><li>
          The encodings in this description are named to match the encodings of
          <a href="sel_p_p_pp.html">SEL (predicates)</a>.
        </li><li>The description of <a href="sel_p_p_pp.html">SEL (predicates)</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul>
    <p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td colspan="4" class="lr">Pm</td><td class="l">0</td><td class="r">1</td><td colspan="4" class="lr">Pg</td><td class="lr">1</td><td colspan="4" class="lr">Pn</td><td class="lr">1</td><td colspan="4" class="lr">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td/><td class="droppedname">S</td><td colspan="2"/><td colspan="4"/><td colspan="2"/><td colspan="4"/><td/><td colspan="4"/><td/><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="MOV_sel_p_p_pp_"/><p class="asm-code">MOV     <a href="#sa_pd" title="Destination scalable predicate register (field &quot;Pd&quot;)">&lt;Pd&gt;</a>.B, <a href="#sa_pg" title="Governing scalable predicate register (field &quot;Pg&quot;)">&lt;Pg&gt;</a>/M, <a href="#sa_pn" title="First source scalable predicate register (field &quot;Pn&quot;)">&lt;Pn&gt;</a>.B</p><p class="equivto">
      is equivalent to
    </p>
          <p class="asm-code"><a href="sel_p_p_pp.html#sel_p_p_pp_">SEL</a> <a href="#sa_pd" title="Destination scalable predicate register (field &quot;Pd&quot;)">&lt;Pd&gt;</a>.B, <a href="#sa_pg" title="Governing scalable predicate register (field &quot;Pg&quot;)">&lt;Pg&gt;</a>, <a href="#sa_pn" title="First source scalable predicate register (field &quot;Pn&quot;)">&lt;Pn&gt;</a>.B, <a href="#sa_pd" title="Destination scalable predicate register (field &quot;Pd&quot;)">&lt;Pd&gt;</a>.B</p>
          <p class="equivto">
          and is the preferred disassembly when
          <span class="pseudocode">Pd == Pm</span>.
        </p>
        </div>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Pd&gt;</td><td><a id="sa_pd"/>
        
          <p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Pg&gt;</td><td><a id="sa_pg"/>
        
          <p class="aml">Is the name of the governing scalable predicate register, encoded in the "Pg" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Pn&gt;</td><td><a id="sa_pn"/>
        
          <p class="aml">Is the name of the first source scalable predicate register, encoded in the "Pn" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="sel_p_p_pp.html">SEL (predicates)</a> gives the operational pseudocode for this instruction.</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
              <ul><li>
                  The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
                </li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
              <ul><li>
                  The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.
                </li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
    </p></body></html>
